Design house (DSP) companies that once focused on outsourced semiconductor design are expanding in both contract pricing and funding scale as AI chip mass production becomes harder with foundry steps alone after 2-nanometre nodes. With physical limits nearing, 2.5D and 3D stacking and chiplets are becoming key, making advanced packaging and interconnect new battlegrounds. Firms are shifting toward integrated design platforms and infrastructure architecture partnerships, alongside rising high-value project shares and larger financings.

The semiconductor industry is shifting its technology race from shrinking process nodes to packaging as scaling approaches physical limits. Companies are increasingly relying on 2.5D and 3D stacking and chiplets to meet performance, power and bandwidth demands, driving changes across the value chain that includes IP, libraries and EDA tools. Memory makers SK hynix and Samsung Electronics are advancing their packaging technologies. Intel has also demonstrated GaN-on-silicon chiplet technology and integration with silicon digital control circuits.