AD Technology will jointly develop customised 4-nanometre-class semiconductors with Germany's Fraunhofer Institute for Integrated Circuits. AD Technology said on Feb. 23 it will pursue a strategic technology partnership with Fraunhofer IIS to jointly develop 4-nanometre-class process-based SoC (System-on-Chip) and chiplet solutions. It aims to respond to growing demand for customised semiconductors in the European market.

The two sides will develop customised semiconductor solutions that meet both high-performance and low-power requirements through design collaboration based on an advanced 4-nanometre-class process. They plan to combine Fraunhofer IIS's expertise in system and algorithm design with AD Technology's capabilities in ASIC design and process optimisation.

The company expects the collaboration to strengthen competitiveness in product differentiation, power optimisation and shorter development times in high value-added industries such as artificial intelligence (AI), the internet of things (IoT) and automobiles. AD Technology has ASIC design service capabilities based on Samsung Foundry processes. Its in-house design optimisation platform, Capella, provides customer-specific libraries optimised for process characteristics.

Albert Heuberger (알버트 호이버거), executive director of Fraunhofer IIS, said, "This is a meaningful example that can accelerate innovation through international cooperation." He added, "By combining the expertise of both sides, we will be able to expand research outcomes into industrial value."

Park Jun-gyu (박준규), CEO of AD Technology, said, "By combining Fraunhofer IIS's research capabilities with our expertise in ASIC and chiplet design, we will provide more advanced semiconductor solutions to European customers." He added, "We will continue to expand strategic partnerships within the global semiconductor ecosystem and strengthen our technology competitiveness."