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Samsung Electronics bets on zHBM by stacking memory on accelerators

Samsung Electronics is preparing a two-track strategy of conventional HBM5 and its zHBM concept as it seeks to regain leadership in high-bandwidth memory. The company is shifting to a design that stacks HBM directly on top of AI accelerators, removing the interposer that links logic and memory side-by-side. Samsung targets 230 percent higher bandwidth and 70 percent lower power than HBM4E. Commercialisation will hinge on heat management and wafer hybrid-bonding yields.

Industry

AMAT says AI chip performance hinges on data movement, solution is 3D scaling

Applied Materials says efficiency in moving data, rather than computing speed, is the main bottleneck for AI semiconductor performance and that the industry solution is 3D scaling. It described 3D scaling across logic, memory and packaging, and said capacity expansion should accompany demand. The company detailed approaches for DRAM, a shift in HBM stacking from micro-bumps to hybrid bonding, and panel interposer development, while highlighting cooperation with Samsung Electronics and SK Hynix in Korea.

Industry

Post-HBM paths diverge as Samsung stacks and SK hynix connects

Samsung Electronics and SK hynix are pursuing different approaches for the next step after high-bandwidth memory, as rising AI workloads make it hard to expand bandwidth and capacity with HBM alone. Samsung is focusing on 3D vertical stacking that places HBM on top of accelerators to reduce data-movement bottlenecks. SK hynix is standardising high-bandwidth flash with SanDisk, linking different memory tiers via UCIe to raise system capacity and efficiency.