[DigitalToday reporter Dae-geon Seok (석대건)] Samsung Electronics has made a new bet to regain the initiative in HBM. It is preparing zHBM on a two-track basis alongside conventional HBM5, targeting the mainstream market in 2028. While TSMC and SK hynix focus on advancing interposers, Samsung aims to leverage its strengths as an integrated device manufacturer to vertically bind logic and memory.

On Sept. 8, the industry said Samsung is shifting to a structure that stacks high-bandwidth memory (HBM) vertically directly on top of an accelerator, instead of placing it alongside an AI accelerator. Samsung recently unveiled a zHBM concept model at FMS (Future of Memory and Storage) 2026 and Semiconductor Architecture Conference 2026. zHBM removes the interposer that connected a logic chip and memory side-by-side and directly attaches the two chips. Samsung’s targets are a 230 percent increase in bandwidth and a 70 percent reduction in power versus HBM4E. The 100 watts saved is redistributed to accelerator computing.

The push toward vertical integration comes as space alongside accelerators has filled up. An interposer is an intermediate silicon substrate that links logic and memory side-by-side. Even if the accelerator chip area increases, its perimeter does not grow proportionally, while required bandwidth rises quickly. To add more HBM, the interposer must be enlarged, but yields fall if it exceeds the area that lithography equipment can draw in a single pass. As the substrate gets bigger, the likelihood of warpage also rises.

zHBM shortens that wiring by turning it vertical. Wiring that ran several millimetres through an interposer is reduced to tens of micrometres or less. Shorter wiring removes the need for input-output circuits that drove long lines, and it also eliminates the section that aligns and outputs data. Most of the power savings come from this. Samsung also applied a method of splitting and placing multiple input-output paths to reduce internal data-movement distances inside HBM.

◆ Wafer hybrid-bonding yields will determine the pace of commercialisation

The process that enables this is wafer-level hybrid bonding. It is a technology that directly bonds copper to copper instead of using conventional microbumps, boosting bonding density by several times in the single-digit range, and it must handle pitches of 6 micrometres or less. Samsung’s plan is to build on its experience with V-NAND stacking and through-silicon vias (TSV) to combine multiple DRAM wafers and compute wafers into a single structure.

In a roadmap Samsung unveiled at Hot Chips 2026, the first phase applies its 4-nanometre process to the base die, the bottom layer of HBM, to move the memory controller from the accelerator to the memory side. In this phase, heat was reduced by 35 percent at peak by applying HPB. The second phase adds a temperature sensor and compute units on the base die. The third phase eliminates the interposer itself.

zHBM sits at the end of Samsung’s memory roadmap. The product now in mass production is HBM4, for which shipments began in February. HBM4E was sampled in May, with mass production targeted for next year. HBM5, which keeps the interposer approach while improving performance, is expected to follow around 2028. zHBM is at a proof-of-concept (PoC) stage, with design verification and collaboration with customers under way, and the industry sees mass production between 2028 and 2029. Mirae Asset Securities analysed that "zHBM presupposes hybrid bonding at pitches of 6 micrometres or less and integrated memory-SoC design, making it something only Samsung Electronics can internalise."

Heat and yield will be the dividing line for commercialisation speed. If memory is placed on top of an accelerator that uses up to 700 to 1,000 watts, that heat rises directly into the memory. In DRAM, as temperature rises, the time it can retain data becomes shorter. Wafer bonding also requires sub-micron alignment precision, and yields fall sharply as more layers are stacked. Ultimately, if either the logic below or the memory above is defective, the entire package must be discarded. For Samsung, securing yields quickly is necessary to cut development costs as well.