Design house (DSP) companies that once focused on outsourced semiconductor design are expanding in both contract pricing and funding scale as AI chip mass production becomes harder with foundry steps alone after 2-nanometre nodes. With physical limits nearing, 2.5D and 3D stacking and chiplets are becoming key, making advanced packaging and interconnect new battlegrounds. Firms are shifting toward integrated design platforms and infrastructure architecture partnerships, alongside rising high-value project shares and larger financings.

AD Technology said on Feb. 23 it will pursue a strategic technology partnership with Germany\'s Fraunhofer Institute for Integrated Circuits (Fraunhofer IIS) to jointly develop 4-nanometre-class process-based SoC and chiplet solutions. The company said the work targets rising demand for customised semiconductors in Europe. It plans to combine Fraunhofer IIS\'s system and algorithm design expertise with its own ASIC design and process optimisation capabilities.