As high-bandwidth memory (HBM) moves beyond 16 layers, a shift in packaging bonding technology is coming into view. Changes are also being detected in the equipment supply chain, which has been built around thermal compression (TC) bonders, with hybrid bonding (HCB) in mind.

Industry sources said on Thursday that the three memory makers are reviewing a plan to introduce hybrid bonding in phases from HBM4 or later generations. That is because limits of existing bonding methods are emerging as HBM stacks move past 16 layers and head higher. Still, the cost burden is large, so a parallel approach with the 'Advanced MR-MUF' process is widely being discussed for the time being.

The equipment sector is also preparing in line with this trend. In the TC bonder market for HBM, Hanmi Semiconductor has effectively monopolised SK Hynix volume, and Hanwha Semitech has recently entered as a new supplier to SK Hynix. In hybrid bonders, global packaging equipment makers ASMPT and BESI have already built up a supply track record for foundry customers. The supply landscape may be adjusted depending on when memory makers choose which equipment makers as mass-production partners.

The core of the technology shift lies in how chips are attached to each other. Existing TC bonding uses micro bumps, small protrusion-type joints, between chips and bonds them with heat and pressure. It is simple and stable, but as chips are stacked, the space taken up by bumps makes the package thicker and lengthens signal transmission distance. This structure shows its limits as HBM layer counts increase.

Hybrid bonding directly joins copper and an insulating layer without bumps. It can keep chip thickness thinner, allowing more layers at the same height, and it is known to be advantageous in data transfer speed, power efficiency and heat generation. But securing yield is difficult because the two surfaces must be flattened to the atomic level for bonding.

This trend is also confirmed in SK Hynix technology presentations. Jonghun Kim (김종훈), an SK Hynix technology leader, said at a semiconductor conference held in Seoul on April 28 that the company has completed technology verification applying hybrid bonding to 12-layer HBM. He said yields at the mass-production stage have improved meaningfully compared with two years ago. But cost competitiveness remains a task, and the company plans to use the MR-MUF process up to 16-layer HBM3E.

Equipment makers also appear to be taking different approaches. As a leading TC bonder supplier, Hanmi Semiconductor is speeding up development of hybrid bonders, while Hanwha Semitech is seeking to expand its next-generation equipment lineup after entering SK Hynix. ASMPT and BESI are being mentioned as possible entrants into the memory segment based on their foundry supply experience. Selection of the first mass-production partners could affect subsequent order flows.

There is also the variable of the base die, the logic chip at the bottom of HBM. SK Hynix is taking a cooperation structure from HBM4 in which it entrusts base-die manufacturing to TSMC. Eugene Investment & Securities, in a recent report, analysed that production stabilisation delays from base-die outsourcing first introduced in HBM4 will be substantially improved in HBM4E. As part of the backend value chain is handled in Taiwan, the scope of benefits for South Korean equipment makers could also be influenced by this trend.

The shift in bonding technology is likely to proceed in phases by generation rather than being carried out all at once in the short term. Eugene Investment & Securities forecast that 2027 HBM price negotiations will be conducted at a high level, taking into account profit margins for commodity DRAM and NAND. As memory makers' profitability is intertwined with the pace of production stabilisation at the timing of the bonding shift, equipment supply-chain trends are expected to follow the same clock.