Intel has signalled a structural shift in the semiconductor memory market by promoting Z-angle Memory (ZAM), a next-generation vertical-stacked memory technology designed to replace conventional high-bandwidth memory (HBM).

On May 13, TechRadar reported that Intel plans to disclose ZAM through a paper for the upcoming VLSI Conference. The technology uses a vertically stacked structure instead of the conventional method of placing chips flat, with the aim of boosting data-transfer speed and reducing power consumption. Intel backs the technology’s development, while Japan-based Saimemory Corporation, a SoftBank subsidiary, is leading commercialisation. It is expected to form a direct competitive lineup with HBM4, which is set to be used in Nvidia’s next-generation AI platform.

A ZAM module is designed with a total of 9 functional layers stacked vertically. A single control layer sits at the top, with 8 DRAM storage layers stacked below it. Each DRAM layer has 1.125 GB of capacity, providing about 9 GB of memory per module excluding overhead. It also implements an ultra-thin design by reducing the thickness of the silicon substrate separating chips to about 3 microns.

To connect the large vertical stack structure reliably, Intel also developed its own fusion bonding process. Three through-silicon vias (TSVs) run through the entire module to connect each layer. It also placed 2 to 3 metal rings on each layer to bind with the TSVs, improving the stability of power and data flow. Intel explained that this helps secure precision and reliability even in high-density structures.

On performance, ZAM is seen as a technology that could reshape the next-generation AI memory market. According to Saimemory’s earlier announcement, ZAM is known to be capable of speeds 2 to 3 times faster than current HBM3. Based on HBM3’s standard bandwidth of 819 GBps, that translates into a total throughput of up to about 2.5 TBps. This is assessed as performance comparable to HBM4, which is set to be used in Nvidia’s Vera Rubin platform.

Still, there are significant hurdles before commercialisation. So far, a working ZAM prototype has not been disclosed through an independent review body or a third-party test lab. The manufacturing process of precisely bonding 8 layers without defects is also seen as a high-difficulty technology that has yet to be industrially verified. Another variable is that a technical edge cannot be guaranteed to lead directly to market success.

Competition with the HBM4 ecosystem, which already has a global supply chain and production roadmap in place, is also emerging as a key task. Without securing broad adoption and support across the industry, it could lose out in standards competition despite strong technical specifications. As a result, the presentation at the VLSI Conference in June is expected to be a major turning point in assessing whether Intel’s ZAM can go beyond a conceptual proposal and be realised as a commercial technology.