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Industry
Samsung Electronics bets on zHBM by stacking memory on accelerators
Samsung Electronics is preparing a two-track strategy of conventional HBM5 and its zHBM concept as it seeks to regain leadership in high-bandwidth memory. The company is shifting to a design that stacks HBM directly on top of AI accelerators, removing the interposer that links logic and memory side-by-side. Samsung targets 230 percent higher bandwidth and 70 percent lower power than HBM4E. Commercialisation will hinge on heat management and wafer hybrid-bonding yields.
AI & Enterprise
SiFive unveils BigSky RISC-V development server, wins hyperscaler customers
RISC-V chip designer SiFive has unveiled its BigSky SF-2U870 development server based on its own CPUs, a report said. The company said the system helps migrate key workloads to the RISC-V open architecture and will be adopted by hyperscalers and software customers. BigSky includes 32 SiFive P870-D cores, 256GB of DDR5 memory, two 7.68TB NVMe SSDs and 10 and 25 Gbps OCP network adapters.
AI & Enterprise
Nvidia begins mass production of Groq 3 LPX for AI agents
Nvidia has shifted its Groq 3 LPX inference accelerator for AI agents into mass production. The chip extends Nvidia\'s Vera Rubin data center platform and targets high-speed token generation to reduce decode latency in agent workflows. In an Artificial Analysis benchmark, it produced 3,400 tokens per second running the open-source Gemma 4 31B model with a 100,000-token context window. Nebius Group is among early adopters, and SpaceX was named a new flagship customer.
