Qualcomm is stepping up its re-entry into the data centre AI chip market with a new memory architecture. It is seeking differentiation in the AI inference market through a new design that uses LPDDR memory instead of high-bandwidth memory (HBM).

On July 1 local time, IT outlet TechRadar reported that Qualcomm unveiled a next-generation memory architecture called High Bandwidth Compute (HBC). It said it plans to release the AI250 AI inference accelerator using the technology in mid-2027.

The core of the technology is a near-memory compute structure that vertically stacks memory directly above the compute chip. Instead of separating memory and the processor, it stacks LPDDR memory directly on the compute die to cut data travel distance and boost bandwidth and power efficiency at the same time. Qualcomm explained that the structure can deliver up to 133TB/s of memory bandwidth.

The company stressed that HBC could be a new alternative in an AI chip market centred on HBM. It said the first-generation HBC supports up to 768GB of memory capacity and, in large-scale AI inference environments, provides up to 6 times higher memory bandwidth per watt than HBM. It said energy efficiency could improve by up to 200 times in mixed inference environments with small and large models, such as code-generation AI. Qualcomm described it as a "technology that eliminates the HBM tax (HBM Tax)."

Some point out, however, that the performance comparisons were not made under identical conditions. While HBM4 is based on pure bandwidth of the memory itself, Qualcomm's figures reflect results for the overall architecture that handles compute and memory together. The industry also says it is difficult to compare the two technologies directly using simple figures alone.

Qualcomm is placing its biggest emphasis on power efficiency. As the spread of generative AI drives a surge in data centre power consumption, power and cooling costs have emerged as the industry's biggest challenge. In that context, Qualcomm aims to secure competitiveness by applying low-power design expertise built up in smartphone chips to data centre AI semiconductors.

It is also strengthening partnerships. Qualcomm named Meta and Microsoft as key partners. It said it signed a multi-year AI collaboration agreement with Meta that uses Qualcomm processors, and that Microsoft is also expanding cooperation with Qualcomm across data centres, PCs and local AI environments. Satya Nadella (사티아 나델라), Microsoft's chief executive officer, has stressed the drive to build efficiency-focused data centres, saying reducing power and water use is an important task in expanding AI infrastructure.

For that reason, Qualcomm's low-power design strategy is being seen as extending beyond a straightforward performance contest and linking to operating cost reductions for major customers.

Competition in memory technology is also expected to intensify. High Bandwidth Flash (HBF), being pursued by Samsung Electronics, SK Hynix and SanDisk, is also being cited as a next-generation memory technology aimed at the AI inference market. In generative AI inference environments where reads account for a large share, the possibility is growing that a variety of memory architectures will compete alongside HBM.

However, the performance and efficiency figures Qualcomm presented have not yet undergone independent external verification. The industry sees how much power efficiency and performance are realised after actual products launch as likely to determine market competitiveness.

Even so, securing cooperation with Meta and Microsoft is being interpreted as a signal that Qualcomm, a strong player in mobile semiconductors, is seeking to expand its presence in the data centre AI chip market as well. Attention is on whether a new competitive landscape will form in an AI chip market centred on Nvidia.