[DigitalToday reporter Jinju Hong (홍진주)] Taiwan's TSMC, the world's largest foundry, unveiled its semiconductor process roadmap through 2029 and newly presented next-generation processes A13, A12 and N2U. A key focus is a strategic shift that goes beyond the race to smaller geometries to include packaging and system expansion.

On April 23 local time, online media outlet Gigazine reported that TSMC adjusted parts of its existing plan and unveiled a new process lineup. The A16 process, originally expected to enter mass production in 2026, was delayed to 2027 to match the product schedules of key customers.

At the center of the roadmap is A13. A13 is a scaled-down version of the existing A14, cutting chip area by about 6 percent while keeping design rules so customers can migrate without major redesigns. Mass production is scheduled for 2029. TSMC plans to improve performance and power efficiency in parallel through optimisation of design and manufacturing collaboration.

TSMC also announced A12 targeting AI and high-performance computing (HPC). A12 is an enhanced process applying back-side power delivery technology, aiming to meet demand for high-performance chips for data centres. In the AI infrastructure market, A16 and A12 are expected to form a core axis in the future.

N2U, an expanded 2-nanometre-family process, will enter mass production in 2028. Compared with N2P, N2U can improve performance by 3 to 4 percent, or cut power consumption by 8 to 10 percent at the same performance. The strategy reflects an effort to lower customers' migration costs by maintaining design-asset compatibility.

In the announcement, TSMC highlighted packaging technology as a core growth pillar alongside process scaling. Its 2.5D stacking technology CoWoS is already being applied to large AI chips, and the company plans to expand it in 2028 to a maximum 14-reticle scale to integrate large compute dies and high-bandwidth memory (HBM) at scale. It also signalled mass production in 2029 of 40-reticle-class system-on-wafer (SoW-X).

3D stacking technology is also evolving. 'A14-to-A14 SoIC' aims to raise chip-to-chip I/O density by about 1.8 times compared with existing technology. 'COUPE on substrate', a next-generation optical technology for data-centre AI acceleration, is set to enter mass production in 2026. TSMC stressed that, compared with detachable optical modules on substrate, the technology doubles power efficiency and cuts latency to one-tenth.

TSMC is also pursuing processes for automotive and robotics. It announced N2A, an automotive process based on nanosheet transistors, and is targeting completion of certification in 2028. N2A aims to deliver 15 to 20 percent faster performance than N3A at the same power, while focusing on meeting automotive reliability standards.

TSMC also unveiled N16HV, a process for display driving. The process extends high-voltage technology to the FinFET generation, and TSMC said it can raise gate density by 41 percent and cut power consumption by 35 percent compared with N28HV. In displays for nearsightedness, it can reduce die area by 40 percent and cut power by more than 20 percent, which could be linked to improved usability of products such as smart glasses.

TSMC's latest roadmap is characterised by differentiating process strategies by customer group. By pairing A13 and N2U, which emphasise design compatibility and ease of transition, with A12 and expanded CoWoS that highlight power-structure and packaging innovations, it made clear it will broaden the competitive axis from simple scaling to the system level.

In the industry, it is being assessed as an example showing that competition in the AI era is shifting from process scaling alone to packaging, power efficiency and large-scale integration capabilities.