Chips&Media on Tuesday unveiled a data compression (DC) IP designed to reduce memory bottlenecks in NPUs, dedicated chips for AI computing, and said it will move to target the AI edge and server markets. It is the company’s first multimedia IP aimed beyond video and compresses feature maps, intermediate data generated during AI processing, without loss.

As AI inference workloads rise rapidly on edge devices and servers, memory bandwidth has emerged as a factor that determines system performance. Data traffic is heavy as feature maps are repeatedly read from and written to external memory such as DRAM. If bandwidth hits its limit, computing units must wait because data does not arrive in time even if NPU performance is sufficient. Frequent memory access also increases power consumption, adding to the burden in mobile and embedded environments.

The data compression IP unveiled by Chips&Media compresses and restores feature maps in real time between the NPU and external memory. It uses a lossless method that restores the original data without loss, so AI model inference accuracy does not decline, the company said.

In tests of major vision networks, memory bandwidth savings were 35.2 percent for FP16, 45.7 percent for BF16 and 53.5 percent for INT8. That means the bandwidth available to the NPU widens by that amount under the same memory conditions, it said.

To make it easy to attach to existing systems, it was designed in an inline AXI bridge structure placed between the AXI bus, a communication standard for data exchange among on-chip components, and the NPU. It is a lightweight structure that uses an existing AXI clock without a separate internal SRAM, minimising increases in hardware area. It supports multiple data formats including INT8, FP16 and BF16, and can also handle line-rate processing to match high-speed data flows.

Hardware implementation is targeted for completion in the first quarter of 2027. Chips&Media plans to expand the lineup from feature maps to static weight compression, and to KV cache compression, which increases memory usage in large language models and vision-language models. It also plans to broaden the scope of application to match customer requirements and AI workload characteristics.

A Chips&Media official said, "Based on hardware IP design capabilities accumulated for more than 20 years and power, area and performance optimisation technology, we will maintain competitiveness in the existing video codec market while expanding our business into the rapidly growing AI and high-performance multimedia IP market." The official added, "Starting with data compression IP, we plan to continuously expand the lineup of video-related IP products and build Chips&Media’s multimedia IP portfolio."