China\'s semiconductor design software industry is moving to support Huawei\'s next-generation chip strategy, with companies developing tools aligned to its Tau Scaling framework and 3D design approach. Empyrean Technology unveiled a 3D IC verification platform, while a Peking University team showed a prototype compatible with Huawei\'s Logic Folding architecture. Industry and research groups say technical hurdles and gaps with U.S.-led full-flow EDA suites mean commercialisation could take 4 to 5 years.

Huawei has set a goal of developing advanced chips at a 1.4 nanometre process level by 2031 and unveiled a new chip design principle it calls the Tau Scaling Law. Bloomberg News reported the company said at a Shanghai semiconductor symposium it aims to make industry-leading semiconductors within the next five years, but did not provide independent performance data. The approach seeks performance gains by reducing signal and data movement time inside chips and systems.